An FPGA implementation of the SURF algorithm for the ExoMars programme

Achieving highly accurate feature extraction in a short period of time is very important for space applications based on computer vision algorithms, such as with the ExoMars programme of ESA. The paper describes a HW/SW co-design scheme using FPGAs to speed-up the SURF algorithm when executed on a low computational power CPU. It performs algorithmic analysis and restructures the SURF steps leading to efficient hardware implementation, while at the same time it exploits the advantages of the CPU. The HW architecture is implemented on a Xilinx Virtex 6 FPGA achieving real-time performance with low hardware cost and highly accurate results.